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?2009 integrated device technology, inc. january 2009 dsc-5638/4 1 functional block diagram features: true dual-ported memory cells which allow simultaneous access of the same memory location high-speed clock to data access ? commercial: 6.5/7.5/9ns (max.) ? industrial: 7.5ns (max.) low-power operation ? idt70v9359/49l active: 450mw (typ.) standby: 1.5mw (typ.) flow-through or pipelined output mode on either port via the ft /pipe pins counter enable and reset features dual chip enables allow for depth expansion without additional logic full synchronous operation on both ports ? 3.5ns setup to clock and 0ns hold on all control, data, and address inputs ? data input, address, and control registers ? fast 6.5ns clock to data out in the pipelined output mode ? self-timed write allows fast cycle time ? 10ns cycle time, 100mhz operation in pipelined output mode separate upper-byte and lower-byte controls for multiplexed bus and bus matching compatibility lvttl- compatible, single 3.3v (0.3v) power supply industrial temperature range (?40c to +85c) is available for 83 mhz available in a 100-pin thin quad flatpack (tqfp) and 100- pin fine pitch ball grid array (fpbga) packages. idt70v9359/49l 0a 1a 0b 1b 0/1 ab i/o control 1 0/1 0 ft /pipe r r/ w r ub r lb r ce 0r oe r ce 1r memory array counter/ address reg. 5638 drw 01 a 12r (1) a 0r clk r ads r cnten r cntrst r i/o 9l -i/o 17l i/o 0l -i/o 8l i/o 9r -i/o 17r i/o 0r -i/o 8r a 0l clk l ads l a 12l (1) cnten l cntrst l counter/ address reg. r/ w l ub l lb l ce 0l oe l ce 1l 1 0/1 0 1b 0b 1a 0a 0/1 ba i/o control ft /pipe l high-speed 3.3v 8/4k x 18 synchronous pipelined dual-port static ram note: 1. a 12 is a nc for idt70v9349.
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 2 description: the idt70v9359/49 is a high-speed 8/4k x 18 bit synchronous dual-port ram. the memory array utilizes dual-port memory cells to allow simultaneous access of any address from both ports. registers on control, data, and address inputs provide minimal setup and hold times. the timing latitude provided by this approach allows systems to be designed with very short cycle times. with an input data register, the idt70v9359/49 has been optimized for applications having unidirectional or bidirectional data flow in bursts. an automatic power down feature, controlled by ce 0 and ce 1, permits the on-chip circuitry of each port to enter a very low standby power mode. fabricated using idt?s cmos high-performance technology, these devices typically operate on only 450mw of power. index 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 17 18 19 20 21 22 23 24 25 75 74 73 72 71 70 69 68 67 66 65 64 63 62 61 60 59 58 57 56 55 54 53 52 51 26 27 28 29 30 31 32 33 34 35 36 37 38 39 40 41 42 43 44 45 46 47 48 49 50 100 99 98 97 96 95 94 93 92 91 90 89 88 87 86 85 84 83 82 81 80 79 78 77 76 100-pin tqfp top view (6) a 9l a 10l a 11l a 12l (1) nc nc nc lb l ub l ce 0l ce 1l cntrst l r/ w l oe l v dd ft /pipe l i/o 16l i/o 17l i/o 15l i/o 14l i/o 13l i/o 12l i/o 11l i/o 10l 5638 drw 02 a 8r a 9r a 10r a 11r a 12r (1) nc nc nc lb r ub r ce 0r cntrst r r/ w r v ss oe r ft /pipe r i/o 14r i/o 13r i/o 12r i/o 11r ce 1r i/o 17r v ss i/o 16r i/o 15r a 8 l a 7 l a 6 l a 5 l a 4 l a 3 l a 2 l a 1 l a 0 l c n t e n l c l k l a d s l v s s v s s a d s r c l k r c n t e n r a 0 r a 2 r a 3 r a 4 r a 5 r a 6 r a 7 r i / o 9 l i / o 8 l v d d i / o 7 l i / o 6 l i / o 5 l i / o 4 l i / o 3 l i / o 2 l i / o 1 l v s s i / o 0 l i / o 4 r i / o 5 r i / o 6 r i / o 3 r i / o 0 r i / o 1 r i / o 2 r i / o 7 r i / o 8 r i / o 9 r i / o 1 0 r a 1 r . 70v9359/49pf pn100-1 (5) v ss v s s v d d 07/03/02 notes: 1. a 12 is a nc for idt70v9349. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. package body is approximately 14mm x 14mm x 1.4mm. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. pin configurations (1,2,3,4)
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 3 70v9359/49bf bf100 (5) 100-pin fpbga top view (6) c10 i/o 3r d8 i/o 8r c8 i/o 11r a9 i/o 10r d9 i/o 5r c9 i/o 7r b9 i/o 9r d10 i/o 1r c7 i/o 15r b8 i/o 12r a8 i/o 13r a10 i/o 17r d7 i/o 14r b7 pl/ ft r a7 vss b6 oe r c6 i/o 16r d6 ce 0r a5 vss b5 r/ w r c5 ce 1r d5 lb r a4 cntrst r b4 c4 a 9r d4 a 2r a3 ub r b3 a 10r c3 a 5r d3 a 1r d2 clk r c2 a 4r b2 a 7r a2 a 11r a1 a 8r b1 a 6r c1 a 3r d1 a 0r e1 vss e2 ads r e3 cnten r e4 a 1l f1 vss f2 clk l f3 a 0l f4 a 3l g1 cnten l g2 a 4l g3 a 7l g4 ub l h1 a 2l h2 a 6l h3 a 11l h4 ce 0l j1 a 5l j2 a 9l j3 j4 r/ w l k1 a 8l k2 a 10l k3 lb l k4 ce 1l a6 vss b10 i/o 6r e5 ads l e6 vss e7 i/o 4r e8 i/o 2r e9 i/o 0r e10 v dd f5 v dd f6 vss f8 i/o 2l f9 i/o 1l f10 i/o 0l g5 vss g6 i/o 13l g7 nc g8 i/o 4l g9 vss g10 i/o 3l h5 cntrst l h6 i/o 15l h7 i/o 9l h8 i/o 7l h9 i/o 6l h10 i/o 5l j5 oe l j6 pl/ ft l j7 i/o 12l j8 i/o 10l j9 vss j10 i/o 8l k5 v dd k6 v dd k7 i/o 16l k8 i/o 14l k9 i/o 11l k10 i/o 17l f7 v dd 5638 drw 03 , a 12r (1) a 12l (1) 07/03/02 notes: 1. a 12 is a nc for idt70v9349. 2. all v dd pins must be connected to power supply. 3. all v ss pins must be connected to ground supply. 4. package body is approximately 10mm x 10mm x 1.4mm with 0.8mm ball pitch. 5. this package code is used to reference the package diagram. 6. this text does not indicate orientation of the actual part-marking. pin configurations(cont'd) (1,2,3,4)
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 4 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ads , cnten , cntrst = x. 3. oe is an asynchronous input signal. truth table i?read/write and enable control (1,2,3) pin names left port right port names ce 0l, ce 1l ce 0r, ce 1r chip enables (3) r/ w l r/ w r read/write enable oe l oe r output enable a 0l - a 12l (1) a 0r - a 12r (1 ) address i/o 0l - i/o 17l i/o 0r - i/o 17r data input/output clk l clk r clock ub l ub r upper byte select (2 ) lb l lb r lower byte select (2 ) ads l ads r address strobe enable cnten l cnten r counter enable cntrst l cntrst r counter reset ft /pipe l ft /pipe r flow-through / pipeline v dd power (3.3v) v ss ground (0v) 5638 tbl 01 oe clk ce 0 (5) ce 1 (5) ub (4) lb (4) r/ w upper byte i/o 9-1 7 lower byte i/o 0-8 mode x h x x x x high-z high-z dese lected?power do wn x x l x x x high-z high-z dese lected?power do wn x l h h h x high-z high-z both bytes deselected x lhlhl data in high-z write to upper byte only x lhhll high-z data in write to lowe r byte only x lhlll data in data in write to both byte s l lhlhh data out high-z read upp er byte only l lhhlh high-z data out read lower byte only l lhllh data out data out read both bytes h x l h x x x high-z high-z outputs disabled 5638 tbl 0 2 note: 1. a 12 is a nc for idt70v9349. 2. lb and ub are single buffered regardless of state of ft /pipe. 3. ce o and ce 1 are single buffered when ft /pipe = v il , ce o and ce 1 are double buffered when ft /pipe = v ih , i.e. the signals take two cycles to deselect. 4 lb and ub are single buffered regardless of state of ft /pipe. 5. ce o and ce 1 are single buffered when ft /pipe = v il . ce o and ce 1 are double buffered when ft /pipe = v ih , i.e. the signals take two cycles to deselect.
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 5 recommended operating temperature and supply voltage recommended dc operating conditions absolute maximum ratings (1) notes: 1. these parameters are determined by device characterization, but are not production tested. 2. 3dv references the interpolated capacitance when the input and output switch from 0v to 3v or from 3v to 0v. 3. c out also references c i/o . capacitance (1) (t a = +25c, f = 1.0mh z ) truth table ii?address counter control (1,2) notes: 1. v il > -1.5v for pulse width less than 10 ns. 2. v term must not exceed v dd +0.3v. notes: 1. stresses greater than those listed under absolute maximum ratings may cause permanent damage to the device. this is a stress rating only and functional operation of the device at these or any other conditions above those indicated in the operational sections of this specification is not implied. exposure to absolute maximum rating conditions for extended periods may affect reliability. 2. v term must not exceed v dd +0.3v for more than 25% of the cycle time or 10ns maximum, and is limited to < 20ma for the period of v term > v dd + 0.3v. notes: 1. this is the parameter t a . this is the "instant on" case temperature. external address previous internal address internal address used clk ads cnten cntrst i/o (3 ) mode an x an l (4 ) xhd i/o (n) external address used xanan + 1 h l (5) hd i/o (n+1) counter enabled?internal address generation x an + 1 an + 1 hh hd i/o (n+1) external address blocked?counter disabled (an + 1 reused) xxa 0 xx l (4 ) d i/o (0) counter reset to address 0 5638 tb l 03 grade ambient temperature (1 ) gnd v dd commercial 0 o c to +70 o c0v3.3v + 0.3v industrial -40 o c to +85 o c0v 3.3v + 0.3v 5638 tbl 04 symbol parameter min. typ. max. unit v dd supply voltage 3.0 3.3 3.6 v v ss ground 0 0 0 v v ih input high voltage 2.0 ____ v dd +0.3v (2 ) v v il input low voltage -0.3 (1 ) ____ 0.8 v 5638 tbl 05 symbol rating commercial & industrial unit v te r m (2) terminal voltage with respect to gnd -0.5 to +4.6 v t bias te m p e r atu re under bias -55 to +125 o c t stg storage te m p e r atu re -65 to +150 o c i out dc output current 50 ma 56 38 tbl 06 symbol parameter conditions (2 ) max. unit c in input capacitance v in = 3dv 9 pf c out (3) output capacitance v out = 3dv 10 pf 5638 tbl 07 notes: 1. "h" = v ih, "l" = v il, "x" = don't care. 2. ce 0 , lb , ub , and oe = v il ; ce 1 and r/ w = v ih . 3. outputs configured in flow-through output mode: if outputs are in pipelined mode the data out will be delayed by one cycle. 4. ads and cntrst are independent of all other signals including ce 0 , ce 1 , ub and lb . 5. the address counter advances if cnten = v il on the rising edge of clk, regardless of all other signals including ce 0 , ce 1 , ub and lb .
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 6 dc electrical characteristics over the operating temperature supply voltage range (3) (v dd = 3.3v 0.3v) dc electrical characteristics over the operating temperature and supply voltage range ( v dd = 3.3v 0.3v) note: 1. at v dd < 2.0v input leakages are undefined. notes: 1. at f = f max , address and control lines (except output enable) are cycling at the maximum frequency clock cycle of 1/t cyc , using "ac test conditions" at input levels of gnd to 3v. 2. f = 0 means no address, clock, or control lines change. applies only to input at cmos level standby. 3. port "a" may be either left or right port. port "b" is the opposite from port "a". 4. v dd = 3.3v, t a = 25c for typ, and are not production tested. i cc dc (f=0) = 90ma (typ). 5. ce x = v il means ce 0x = v il and ce 1x = v ih ce x = v ih means ce 0x = v ih or ce 1x = v il ce x < 0.2v means ce 0x < 0.2v and ce 1x > v dd - 0.2v ce x > v dd - 0.2v means ce 0x > v dd - 0.2v or ce 1x < 0.2v "x" represents "l" for left port or "r" for right port. symbol parameter test conditions 70v9359/49l unit min. max. |i li | input leakage current (1) v dd = 3.6v, v in = 0v t o v dd ___ 5a |i lo | output leakage current ce = v ih or ce 1 = v il , v out = 0v t o v dd ___ 5a v ol output low voltage i ol = +4ma ___ 0.4 v v oh output high voltage i oh = -4ma 2.4 ___ v 5638 tb l 0 8 70v9359/49l6 com'l only 70v9359/49l7 com'l & ind 70v9359/49l9 com'l only symbol parameter test condition version typ. (4) max. typ. (4 ) max. typ. (4 ) max. unit i dd dynamic operating current (both ports active) ce l and ce r = v il , outputs disabled, f = f max (1 ) com'l l 175 330 155 280 135 230 ma ind l ____ ____ 155 330 ____ ____ i sb1 standby current (both ports - ttl level inputs) ce l = ce r = v ih f = f max (1 ) com'l l 50 80 40 70 30 60 ma ind l ____ ____ 40 80 ____ ____ i sb2 standby current (one port - ttl level inputs) ce "a" = v il and ce "b" = v ih (5 ) active port outputs disabled, f=f max (1 ) com'l l 115 185 105 170 95 155 ma ind l ____ ____ 105 180 ____ ____ i sb3 full standby current (both ports - cmos level inputs) both ports ce l and ce r > v dd - 0.2v, v in > v dd - 0.2v or v in < 0.2v, f = 0 (2 ) com'l l 0.5 3.0 0.5 3.0 0.5 3.0 ma ind l ____ ____ 0.5 3.0 ____ ____ i sb4 full standby current (one port - cmos level inputs) ce "a" < 0.2v and ce "b" > v dd - 0.2v (5) v in > v dd - 0.2v or v in < 0.2v, active port, outputs disabled, f = f max (1 ) com'l l 105 175 95 160 85 145 ma ind l ____ ____ 95 175 ____ ____ 5638 tbl 09
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 7 ac test conditions figure 1. ac output test load. figure 3. typical output derating (lumped capacitive load). 1 2 3 4 5 6 7 8 20 40 100 60 80 120 140 160 180 200 tcd 1 , tcd 2 ( typical, ns) capacitance (pf) 5638 drw 06 -1 0 - 10pf is the i/o capacitance of this device, and 30pf is the ac test load capacitance . input pulse le vels input ris e/fall time s input timing re fe rence le vels output reference levels output load gnd to 3.0v 2ns max. 1.5v 1.5v figures 1, 2, and 3 5638 tbl 10 5638 drw 05 590 ? 30pf 435 ? 3.3v data out 590 ? 5pf* 435 ? 3.3v data out 5638 drw 04 . figure 2. output test load (for t cklz , t ckhz , t olz , and t ohz ). *including scope and jig.
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 8 ac electrical characteristics over the operating temperature range (read and write cycle timing) (3) ( v dd = 3.3v 0.3v, t a = 0c to +70c) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). this parameter is guarant eed by device characteriza- tion, but is not production tested. 2. the pipelined output parameters (t cyc2 , t cd2 ) apply to either or both the left and right ports when ft /pipe = v ih . flow-through parameters (t cyc1 , t cd1 ) apply when ft /pipe = v il for that port. 3. all input signals are synchronous with respect to the clock except for the asynchronous output enable ( oe ), ft /pipe r , and ft /pipe l . 70v9359/49l6 com'l only 70v9359/49l7 com'l & ind 70v9359/49l9 com'l only symbol parameter min.max.min.max.min.max.unit t cyc1 clock cycle time (flow-through) (2) 19 ____ 22 ____ 25 ____ ns t cyc2 clock cycle time (pipelined) (2) 10 ____ 12 ____ 15 ____ ns t ch1 clock high time (flow-through) (2) 6.5 ____ 7.5 ____ 12 ____ ns t cl 1 clock low time (flow-through) (2) 6.5 ____ 7.5 ____ 12 ____ ns t ch2 clock high time (pipelined) (2) 4 ____ 5 ____ 6 ____ ns t cl 2 clock low time (pipelined) (2) 4 ____ 5 ____ 6 ____ ns t r clock rise time ____ 3 ____ 3 ____ 3ns t f clock fall time ____ 3 ____ 3 ____ 3ns t sa address setup time 3.5 ____ 4 ____ 4 ____ ns t ha address hold time 0 ____ 0 ____ 1 ____ ns t sc chip enable setup time 3.5 ____ 4 ____ 4 ____ ns t hc chip enable hold time 0 ____ 0 ____ 1 ____ ns t sb byte enable setup time 3.5 ____ 4 ____ 4 ____ ns t hb byte enable hold time 0 ____ 0 ____ 1 ____ ns t sw r/ w setup time 3.5 ____ 4 ____ 4 ____ ns t hw r/ w hold time 0 ____ 0 ____ 1 ____ ns t sd input data setup time 3.5 ____ 4 ____ 4 ____ ns t hd input data hold time 0 ____ 0 ____ 1 ____ ns t sad ads setup time 3.5 ____ 4 ____ 4 ____ ns t ha d ads hold time 0 ____ 0 ____ 1 ____ ns t scn cnten setup time 3.5 ____ 4 ____ 4 ____ ns t hcn cnten hold time 0 ____ 0 ____ 1 ____ ns t srst cntrst setup time 3.5 ____ 4 ____ 4 ____ ns t hrst cntrst hold time 0 ____ 0 ____ 1 ____ ns t oe output enable to data valid ____ 6.5 ____ 7.5 ____ 9ns t olz output enable to output low-z (1) 2 ____ 2 ____ 2 ____ ns t ohz output enable to output high-z (1) 17 17 17ns t cd1 clock to data valid (flow-through) (2) ____ 15 ____ 18 ____ 20 ns t cd2 clock to data valid (pipelined) (2) ____ 6.5 ____ 7.5 ____ 9ns t dc data output hold after clock high 2 ____ 2 ____ 2 ____ ns t ckhz clock high to output high-z (1) 292929ns t cklz clock high to output low-z (1) 2 ____ 2 ____ 2 ____ ns port-to-port delay t cwdd write port clock high to read data delay ____ 24 ____ 28 ____ 35 ns t ccs clock-to-clock setup time ____ 9 ____ 10 ____ 15 ns 5638 tbl 1 1
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 9 timing waveform of read cycle for flow-through output ( ft /pipe "x" = v il ) (3,7) timing waveform of read cycle for pipelined operation ( ft /pipe "x" = v ih ) (3,7) an an + 1 an + 2 an + 3 t cyc1 t ch1 t cl1 r/ w address data out ce 0 clk oe t sc t hc t cd1 t cklz qn qn + 1 qn + 2 t ohz t olz t oe t ckhz 5638 drw 07 (1) (1) (1) (1) (2) ce 1 ub , lb t sb t hb t sw t hw t sa t ha t dc t dc (5) t sc t hc t sb t hb an an + 1 an + 2 an + 3 t cyc2 t ch2 t cl2 r/ w address ce 0 clk ce 1 ub , lb (4) data out oe t cd2 t cklz qn qn + 1 qn + 2 t ohz t olz t oe 5638 drw 08 (1) (1) (1) (2) t sc t hc t sb t hb t sw t hw t sa t ha t dc t sc t hc t sb t hb (5) (1 latency) (6) (6) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. oe is asynchronously controlled; all other inputs are synchronous to the rising clock edge. 3. ads = v il , cnten and cntrst = v ih . 4. the output is disabled (high-impedance state) by ce 0 = v ih , ce 1 = v il following the next rising edge of the clock. refer to truth table 1. 5. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 6. if ub or lb was high, then the upper byte and/or lower byte of data out for qn + 2 would be disabled (high-impedance state). 7. "x' here denotes left or right port. the diagram is with respect to that port.
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 10 timing waveform with port-to-port flow-through read (4,5,7) timing waveform of a bank select pipelined read (1,2) t sc t hc ce 0(b1) address (b1) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha clk 5638 drw 09 q 0 q 1 q 3 data out(b1) t ch2 t cl2 t cyc2 (3) address (b2) a 0 a 1 a 2 a 3 a 4 a 5 t sa t ha ce 0(b2) data out(b2) q 2 q 4 t cd2 t cd2 t ckhz t cd2 t cklz t dc t ckhz t cd2 t cklz (3) (3) t sc t hc (3) t ckhz (3) t cklz (3) t cd2 a 6 a 6 t dc t sc t hc t sc t hc data in "a" clk "b" r/ w "b" address "a" r/ w "a" clk "a" address "b" no match match no match match valid t cwdd t cd1 t dc data out "b" 5638 drw 10 valid valid t sw t hw t sa t ha t sd t hd t hw t cd1 t ccs t dc t sa t sw t ha (6) (6) notes: 1. b1 represents bank #1; b2 represents bank #2. each bank consists of one idt70v9359/49 for this waveform, and are setup for de pth expansion in this example. address (b1) = address (b2) in this situation. 2. ub , lb , oe , and ads = v il ; ce 1(b1) , ce 1(b2) , r/ w , cnten , and cntrst = v ih . 3. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 4. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . 5. oe = v il for the right port, which is being read from. oe = v ih for the left port, which is being written to. 6. if t ccs < maximum specified, then data from right port read is not valid until the maximum specified for t cwdd . if t ccs > maximum specified, then data from right port read is not valid until t ccs + t cd1 . t cwdd does not apply in this case. 7. all timing is the same for both left and right ports. port "a" may be either left or right port. port "b" is the opposite fro m port "a".
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 11 timing waveform of pipelined read-to-write-to-read ( oe = v il ) (3) timing waveform of pipelined read-to-write-to-read ( oe controlled) (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5638 drw 11 qn qn + 3 data out ce 1 ub , lb t cd2 t ckhz t cklz t cd2 t sc t hc t sb t hb t sw t hw t sa t ha t ch2 t cl2 t cyc2 read nop read t sd t hd (4) (2) (1) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 data in dn + 3 dn + 2 ce 0 clk 5638 drw 12 data out qn qn + 4 ce 1 ub , lb oe t ch2 t cl2 t cyc2 t cklz (1) t cd2 t ohz (1) t cd2 t sd t hd read write read t sc t hc t sb t hb t sw t hw t sa t ha (4) (2) t sw t hw
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 12 timing waveform of flow-through read-to-write-to-read ( oe = v il ) (3) timing waveform of flow-through read-to-write-to-read ( oe controlled) (3) notes: 1. transition is measured 0mv from low or high-impedance voltage with the output test load (figure 2). 2. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 3. ce 0 , ub , lb , and ads = v il ; ce 1 , cnten , and cntrst = v ih . "nop" is "no operation". 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. "nop" is "no operation." data in memory at the selected address may be corrupted and should be re-written to guarantee data i ntegrity. r/ w address an an +1 an + 2 an + 2 an + 3 an + 4 data in dn + 2 ce 0 clk 5638 drw 13 qn data out ce 1 ub , lb t cd1 qn + 1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t cd1 t dc t ckhz qn + 3 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read nop read t cklz (4) (2) (1) (1) t sw t hw write (5) r/ w address an an +1 an + 2 an + 3 an + 4 an + 5 (4) data in dn + 2 ce 0 clk 5638 drw 14 qn data out ce 1 ub , lb t cd1 t ch1 t cl1 t cyc1 t sd t hd t cd1 t dc qn + 4 t cd1 t dc t sc t hc t sb t hb t sw t hw t sa t ha read write read t cklz (2) dn + 3 t ohz (1) (1) t sw t hw oe t oe
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 13 timing waveform of pipelined read with address counter advance (1) timing waveform of flow-through read with address counter advance (1) notes: 1. ce 0 , oe , ub , and lb = v il ; ce 1 , r/ w , and cntrst = v ih . 2. if there is no address change via ads = v il (loading a new address) or cnten = v il (advancing the address), i.e. ads = v ih and cnten = v ih , then the data output remains constant for subsequent clocks. address an clk data out qx - 1 (2) qx qn qn + 2 (2) qn + 3 ads cnten t cyc2 t ch2 t cl2 5638 drw 15 t sa t ha t sad t had t cd2 t dc read external address read with counter counter hold t sad t had t scn t hcn read with counter qn + 1 address an clk data out qx (2) qn qn + 1 qn + 2 qn + 3 (2) qn + 4 ads cnten t cyc1 t ch1 t cl1 5638 drw 16 t sa t ha t sad t had read external address read with counter counter hold t cd1 t dc t sad t had t scn t hcn read with counter
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 14 address (4) an d 0 t ch2 t cl2 t cyc2 q 0 q 1 0 clk data in r/ w cntrst 5638 drw 18 internal (3) address ads cnten t srst t hrst t sd t hd t sw t hw counter reset write address 0 read address 0 read address 1 read address n qn an + 1 an + 2 read address n+1 data out (5) t sa t ha 1 an an + 1 (6) ax t sad t had t scn t hcn (6) timing waveform of write with address counter advance (flow-through or pipelined outputs) (1) timing waveform of counter reset (pipelined outputs) (2) address an clk data in dn dn + 1 dn + 1 dn + 2 ads cnten (7) t ch2 t cl2 t cyc2 5638 drw 17 internal (3) address an (7) an + 1 an + 2 an + 3 an + 4 dn + 3 dn + 4 t sa t ha t sad t had write counter hold write with counter write external address write with counter t sd t hd notes: 1. ce 0 , ub , lb , and r/ w = v il ; ce 1 and cntrst = v ih . 2. ce 0 , ub , lb = v il ; ce 1 = v ih . 3. the "internal address" is equal to the "external address" when ads = v il and equals the counter output when ads = v ih . 4. addresses do not have to be accessed sequentially since ads = v il constantly loads the address on the rising edge of the clk; numbers are for reference use only. 5. output state (high, low, or high-impedance) is determined by the previous cycle control signals. 6. no dead cycle exists during counter reset. a read or write cycle may be coincidental with the counter reset cycle. addr 0 will be accessed. extra cycles are shown here simply for clarification. 7. cnten = v il advances internal address from ?an? to ?an +1?. the transition shown indicates the time required for the counter to advance. the ?an +1? address is written to during this cycle.
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 15 depth and width expansion the idt70v9359/49 features dual chip enables (refer to truth table i) in order to facilitate rapid and simple depth expansion with no require- ments for external logic. figure 4 illustrates how to control the varioius chip enables in order to expand two devices in depth. the idt70v9359/49 can also be used in applications requiring expanded width, as indicated in figure 4. since the banks are allocated at the discretion of the user, the external controller can be set up to drive the input signals for the various devices as required to allow for 36-bit or wider applications. 5638 drw 19 idt70v9359/49 ce 0 ce 1 ce 1 ce 0 ce 0 ce 1 a 13 /a 12 (1) ce 1 ce 0 v dd v dd idt70v9359/49 idt70v9359/49 idt70v9359/49 control inputs control inputs control inputs control inputs cntrs t clk ads cnten r/ w lb , ub oe figure 4. depth and width expansion with idt70v9359/49 functional description the idt70v9359/49 provides a true synchronous dual-port static ram interface. registered inputs provide minimal set-up and hold times on address, data, and all critical control inputs. all internal registers are clocked on the rising edge of the clock signal, however, the self-timed internal write pulse is independent of the low to high transition of the clock signal. an asynchronous output enable is provided to ease asynchronous bus interfacing. counter enable inputs are also provided to stall the operation of the address counters for fast interleaved memory applications. ce 0 = v il and ce 1 = v ih for one clock cycle will power down the internal circuitry to reduce static power consumption. multiple chip enables allow easier banking of multiple idt70v9359/49's for depth expansion configurations. when the pipelined output mode is enabled, two cycles are required with ce 0 = v il and ce 1 = v ih to re-activate the outputs. note: 1. a 13 is for idt70v9359, a 12 is for idt70v9349.
6.42 idt70v9359/49l high-speed 3.3v 8/4k x 18 dual-port synchronous pipelined static ram industrial and commercial temperature range s 16 ordering information a power 99 speed a package a process/ temperature range blank i (1) commercial (0 cto+70 c) industrial (-40 cto+85 c) pf bf 100-pin tqfp (pn100-1) 100-pin fpbga (bf100) 6 7 9 xxxxx device type speed in nanoseconds 5638 drw 20 l low power 70v9359 70v9349 144k (8k x 18-bit) synchronous dual-port ram 72k (4k x 18-bit) synchronous dual-port ram commercial & industrial commercial only . . commercial only the idt logo is a registered trademark of integrated device technology, inc. corporate headquarters for sales: for tech support: 6024 silver creek valley road 800-345-7015 or 408-284-8200 408-284-2794 san jose, ca 95138 fax: 408-284-2775 dualporthelp@idt.com www.idt.com datasheet document history 10/01/01: initial public release 7/3/02 : page 2 & 3 added data revision for pin configurations consolidated multiple devices into one datasheet 08/15/03: removed preliminary status page 16 added idt clock solution table 01/29/09: page 16 removed "idt" from orderable part number note: 1. contact your local sales office for industrial temp range for other speeds, packages and powers. idt dual-port part number dual-port i/o specitications clock specifications idt pll clock device idt non-pll clock device voltage i/o input capacitance input duty cycle requirement maximum frequency jitter tolerance 70v9359/49 3.3 lvttl 9pf 40% 100 150ps idt2305 idt2308 idt2309 fct3805 fct3805d/e fct3807 fct3807d/e 5638 tbl 12 idt clock solution for idt70v9359/49 dual-port

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